1. Field of the Invention
The present invention relates to a semiconductor device having a thin-walled portion formed by electrochemical etching and to a method of fabricating such a semiconductor device.
2. Description of the Related Art
A known semiconductor pressure sensor is fabricated by forming a thin-walled portion in a part of a silicon substrate serving as a semiconductor substrate. The thin-walled portion is used as a diaphragm. Diffused resistors are formed on this diaphragm. The resistance values of these diffused resistors are varied in response to the pressure applied to the diaphragm by a piezoresistance effect. These diffused resistors are connected together to form a bridge circuit via an interconnection pattern. When a pressure is applied to the diaphragm, the bridge circuit is off balance and produces a voltage signal corresponding to the pressure.
In order that the aforementioned sensor detects a pressure accurately, the diaphragm is formed by anisotropic etching processing that relies on an electrochemically stopped etching method showing good controllability about the thickness of the diaphragm. In this electrochemically stopped etching method, anisotropic etching is done within aqueous solution of potassium hydroxide or the like while a predetermined reverse voltage is applied across a portion corresponding to the diaphragm. A depletion layer is produced by the application of the reverse voltage. As the etching progresses, the depletion layer becomes exposed to an etchant. As a result, an electrical current is induced. Thus, the etching is stopped. Using this phenomenon, a diaphragm having a desired thickness is obtained.
A monolithically integrated pressure-detecting circuit may be formed on a chip of a pressure sensor. In this construction, when electrochemically stopped etching is performed as described above, preventing the current from flowing into the integrated pressure-detecting circuit is necessary. Accordingly, in one conventional structure, a diode structure is inserted in a path going from the integrated circuit to the diffused resistors of the diaphragm, thus preventing the inflow of the electrical current to the integrated pressure-detecting circuit.
FIG. 15 shows one sensor chip 1, or semiconductor pressure sensor, of a multiplicity of pressure sensors formed on a silicon wafer. Diffused resistors 3 (see FIG. 16) exhibiting a piezoresistance effect are formed on a diaphragm portion 2. The detection signals from diffused resistors 3 are processed by an integrated circuit 4. A conductor pattern 5 to feed voltage during etching is formed along scribe lines at the outer periphery of the sensor chip 1. The conductor pattern 5 is connected via a diode portion 6a with a conductor pattern 7 on the side of the diaphragm portion 2. The integrated circuit 4 is connected with the conductor pattern 7 through a conductor pattern 4a, a power supply pad 4b, and a diode portion 6b.
As shown in the cross-sectional view of FIG. 16, lateral p-n-p transistors are used as the diode portions 6a and 6b so that an electrical current flows near the surface of the sensor chip 1. An n-type epitaxial layer 1b is formed on a p-type silicon substrate 1a forming the sensor chip 1. This epitaxial layer 1b is divided into a diaphragm region 9 and diode regions 10a, 10b by p-type diffused, isolating regions 8.
Heavily doped, n-type buried layers 11a and 11b are formed in the diode regions 10a and 10b, respectively. Also, p-type diffused collector regions 12a, 12b and p-type emitter regions 13a, 13b are formed in the diode regions 10a and 10b, respectively. These diode regions 10a and 10b are used as base regions. Heavily doped n-type diffused regions 14a and 14b are formed in these base regions, respectively, to make contacts with the conductor pattern 7. The diffused collector regions 12a and 12b surround the diffused emitter regions 13a and 13b, respectively. The conductor pattern 5 formed along the outer periphery of the sensor chip 1 is connected with the diffused emitter region 13a of the diode portion 6a. The conductor pattern 7 is disposed so that the diffused collector region 12a, 12b and the heavily doped n-type diffused region 14a, 14b are shorted to each other.
In the above-described structure, numerous sensor chips (such as the chip 1) are formed. When the rear side of the diaphragm portion 2 of each sensor chip 1 is etched away, an external power supply 16 applies a positive voltage from the voltage-applying conductor pattern 5 to the diaphragm portion 2 via the diode portion 6a. At this time, the diode portion 6b prevents an electrical current from flowing into the integrated circuit 4. Consequently, etching can be carried out while immersing the sensor chips 1, or silicon wafer, in an etchant within an etch bath (not shown). During this process, a voltage is applied between the silicon wafer, or the sensor chips 1, and a counter electrode 17.
When the silicon wafer is cut into individual sensor chips 1 for use, a voltage is applied from the power supply pad 4b to the diffused resistors 3 on the diaphragm portion 2. Also, in this case, the diode portion 6a prevents an electrical current from flowing into the conductor pattern 5.
The diode portion 6b of the above-described prior art construction produces the following troubles. When the diaphragm portion 2 is left as a thick film by electrochemically stopped etching processing, it is necessary to increase the applied voltage so that the depletion layer is widened. Because the diode portion 6b is constructed as shown in FIGS. 17 and 18, the n-type diode region 10b becoming a base region exists just under the conductor pattern 4a via an insulating film 18, the conductor pattern 4a being electrically connected with the diffused emitter region 13b. Therefore, if a positive voltage is applied to this conductor pattern 7 via the diode portion 6a, an inversion layer is formed in a surface layer of the n-type diode region 10b. This becomes channels 19a and 19b (FIG. 19), thus completing a p-channel MOS transistor that electrically connects the p-type diffused collector region 12b with the p-type diffused emitter region 13b or with the diffused isolating regions 8.
This is described in further detail below. As shown in FIG. 16, when a high voltage is applied to the conductor pattern 5 from the external power supply 16, this voltage is impressed on the conductor pattern 7 connected with the diode portion 6b via the diode portion 6a. Since the collector region 12b and n-type diffused region 14b are connected with the conductor pattern 7, the potential in the diode region 10b of the diode portion 6b is raised via this n-type diffused region 14b. Because the conductor pattern 4a located over the diode region 10b is maintained at a low potential, the resulting potential difference creates an inversion layer near the surface of the diode region 10b. In this way, a parasitic transistor is formed on the diode portion 6b. As a result, an electrical current leaks into the integrated circuit 4 through a path from the diffused collector region 12b located under the conductor pattern 4a to the diffused emitter region 13b via the channel inversion layer.
Also, an electrical current leaks from other than the diaphragm portion 2 through a path that goes from the diffused collector region 12b to the silicon substrate 1a via the channel and via the diffused isolating region 8. Therefore, the operation of the diode portion 6b is hindered. This makes the electrochemically stopped etching processing unreliable. In the past, therefore, performing the electrochemically stopped etching processing by applying a high voltage has been difficult. The actual situation is that, when this structure of a diode is adopted, it is substantially impossible to apply a voltage higher than approximately 15 V.